Communication semiconductor integrated circuit, a wireless communication apparatus, and a loop gain calibration method

ABSTRACT

A polar-loop wireless communication apparatus includes, on a forward path between an amplitude detector and a power amplifier which constitute an amplitude control loop, a variable gain amplifier and a switch to change characteristics of a loop filter to output a frequency bandwidth of the amplitude control loop to an order less than an order for normal operation. The system is operated with the characteristics set to the lower order to measure outputs from the power amplifier to calibrate the output power of the power transmitter, and the register is operated with the characteristics set to the higher order to measure the open loop gain of the amplitude control. According to results of the calculation, data to correct gain characteristics of the variable gain amplifier with respect to an output control signal is stored in a nonvolatile memory of a baseband circuit.

CROSS-REFERENCE TO RELATED APPLICATION

The present application relates to subject matters described in the U.S.patent applications being file based on the United Kingdom PatentApplications No. 0212737.1 filed on May 31, 2002, No. 0212729.8 filed onMay 31, 2002, No. 0212723.1 filed on May 31, 2002, No. 0212735.5 filedon May 31, 2002, and No. 0212732.2 filed on May 31, 2002. All of thoseU.S. applications are assigned to the same assignees of the presentapplication.

BACKGROUND OF THE INVENTION

The present invention relates to a technique for improvingcontrollability of output power using a power control signal in ahigh-frequency power amplifier circuit and for calibrating variation ordispersion in a characteristic thereof due to deviation of a gain of anamplifier control loop, and in particular, to a technique effectivelyapplicable to a communication semiconductor integrated circuit includinga phase detecting or detector circuit and an amplifier detecting circuitand to a wireless or radio communication apparatus such as a portabletelephone including the wireless communication apparatus.

One of the systems for wireless communication apparatuses (mobilecommunication apparatuses) such as a portable telephone of the prior artis a global system for mobile communication (GSM) adopted in Europe.This system uses a phase modulation method called a Gaussian MinimumShift Keying (GMSK) method in which a phase of a carrier wave or acarrier signal is shifted according to transmission data.

In general, a transmission output section of a wireless communicationapparatus includes a high-frequency power amplifier circuit, and someGSM wireless communication apparatuses of the prior art are configuredas below. To obtain output power required for a telephone call, a biasvoltage of the high-frequency power amplifier is controlled by a controlvoltage outputted from a circuit called “automatic power control (APC)circuit” which generates a control signal of transmitting ortransmission power according to a signal from a detector to detecttransmitting or transmission power and a transmission request level froma baseband LSI.

Incidentally, for recent portable telephones, a system of enhanced datarates for GSM evolution (EDGE) has been proposed, the EDGE system havinga dual-mode communicating function in which an audio signal iscommunicated in the GMSK modulation and data is communicated in 3π/8rotating 8-PSK (phase shift keying) modulation. The 8-PSK modulation isa modulation implemented by adding, for example, amplitude shift to thecarrier phase shift of the GMSK modulation. In comparison with the GMSKmodulation in which information of one bit is transmitted per symbol,information of three bits is transmitted per symbol in the 8-PSKmodulation. Therefore, a higher transmission rate can be used forcommunication in the EDGE than in the GSM.

As a method to implement a modulation method in which each of a phasecomponent and an amplitude component of a transmitting or transmissionsignal contain information, there has been heretofore known a methodcalled “polar loop” in which a signal to be transmitted is divided intoa phase component and an amplitude component, a feedback operation isconducted for the components respectively by a phase component loop andan amplitude component loop, and signals resultant from the feedbackoperations are mixed with each other by an amplifier to output a signal(described, for example, in page 162 of “High Linearity RF AmplifierDesign” written by Peter B. Kenington and published from ARTECH HOUSE,INC. in 1979).

Since it is necessary in the GSM communication system to output aphase-modulated signal according to a requested output level, ahigh-frequency power amplifier circuit in a final stage can be operatedin a saturation range. In contrast therewith, in a wirelesscommunication system capable of conducting communication in the EDGEmethod, the high-frequency power amplifier circuit in the final stagemust be operated in a non-saturation range. However, in a drive methodto drive a high-frequency power amplifier circuit used in the GSMcommunication system of the prior art, it is difficult to keep linearityrequired for the high-frequency power amplifier circuit in a region of alow output level. In comparison with this method, the polar loop methodis advantageous: the request of linearity for the high-frequency poweramplifier circuit can be satisfied and power efficiency in a low outputlevel range can also be improved.

SUMMARY OF THE INVENTION

In this situation, the inventors of the present invention discussedadoption of the polar loop method in the EDGE wireless communicationsystem. As a result, there has been detected a problem that when the8-PSK modulation is carried out in the polar loop method, it isdifficult to satisfy requirements of specifications of, for example,precision of modulation for a transmission waveform (error vectormagnitude (EVM)) and a degree of noise suppression.

Specifically, there is a problem in which while the modulating precisionis higher and a characteristic called “spectral re-growth” indicating adegree of waveform distortion becomes better when the frequencybandwidth of the amplitude control loop (a frequency range from acentral frequency of the transmission carrier wave to a frequencythereof for which an open loop gain is 0 decibel (dB)) is wider,attenuation of the amplitude control loop becomes smaller for areceiving or reception frequency apart from 20 megaherz (MHz) from thecentral frequency of the transmission carrier wave and a sufficientdegree of noise suppression cannot be obtained when the bandwidth iswide.

In addition, in two feedback loops, the loop gain particularly of theamplifier control loop varies due to dispersion or variation incharacteristics of constituent components in production and hencestability of the loop decreases, and hence it is difficult to obtain adesired output level in a specified or predetermined period of time. Ithas been also detected that the system of the polar loop has a problemthat when an output control operation is conducted for the amplitudemodulation in the amplitude control loop, the gain of the amplitudecontrol loop changes to reduce a phase margin and hence stability of theloop is lowered.

It is therefore an object of the present invention to improve themodulating precision of a transmission waveform and the spectralre-growth and to sufficiently suppress noise in a receiving frequencybandwidth in a wireless communication apparatus such as a portabletelephone having a function to conduct phase modulation and amplitudemodulation.

Another object of the present invention is to provide a reliablewireless communication apparatus which prevents degradation in stabilityof a loop due to variation in a loop gain caused by dispersion incharacteristics of constituent components in production.

Still another object of the present invention is to provide a reliablewireless communication apparatus which prevents, when an output controloperation is conducted for amplitude modulation, degradation instability of a loop due to decrease in a phase margin caused byvariation in an amplitude control loop gain.

An outline of representative aspects of the present invention is asfollows.

In a wireless communication apparatus of polar loop type having a phasecontrol loop to control a phase of a carrier wave or signal outputtedfrom a transmission oscillator and an amplitude control loop to controlamplitude of a transmission output signal outputted from a poweramplifier circuit, there are disposed, on a forward path from anamplifier detector circuit to a power amplifier circuit which constitutethe amplifier control loop, a variable gain amplifier circuit and aswitching unit capable of conducting a change-over of a characteristicof a loop filter for a frequency bandwidth of the amplitude control loopto a degree lower than a degree of the filter in an ordinary operation.While the system is being operated in a state in which the loop filtercharacteristic is changed to the lower-degree filter characteristic, theoutput from the power amplifier is measured in this state to calculatevariation in the gain of the amplifier loop. According to a result ofthe calculation, there is obtained data to calibrate or to correct thegain characteristic of the variable gain amplifier circuit with respectto an output control signal in order to reduce the variation. Thecorrection or corrective data thus obtained is stored in a nonvolatilememory in a baseband large scale integration (LSI) chip. Resultantly, bychanging the loop filter characteristic to the lower-degree filtercharacteristic, the measurement can be conducted when the amplitudecontrol loop is in a more stable state. Additionally, by correcting thegain characteristic of the variable gain amplifier circuit with respectto an output control signal according to the correction data beforehandmeasured and stored in the nonvolatile memory, it is possible tocalibrate or to correct the variation in the gain of the amplitudecontrol loop caused by the dispersion in characteristics of constituentcomponents in production.

According to the present invention, there is provided a wirelesscommunication apparatus of polar loop type having a phase control loopto control a phase of a carrier wave outputted from a transmissionoscillator and an amplitude control loop to control amplitude of atransmission output signal outputted from a power amplifier circuit. Avariable gain amplifier circuit is disposed in a feedback path from atransmission output level detector circuit to an amplitude detectorcircuit which constitute the amplitude control loop. A variable gainamplifier circuit is disposed also in a forward path from the amplitudedetector circuit to the power amplifier circuit of the loop. Gains ofthe variable gain amplifier circuits are controlled in mutually opposingdirections and the sum of gain of the power amplifier circuit and gainrespectively of the variable gain amplifier circuits is controlled to befixed regardless of the output control signal. As a result, even whenthe output power is changed, the open loop gain of the amplitude controlloop can be kept fixed. This prevents the degradation of stability ofthe loop due to the variation or deviation in the loop gain.

Other objects, features and advantages of the invention will becomeapparent from the following description of the embodiments of theinvention taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an outline of a configuration of atransmitting circuit of polar loop type in an embodiment of the presentinvention and an example of a configuration of a wireless communicationsystem using the transmitting circuit;

FIG. 2 is a graph showing an open loop gain characteristic of anamplitude control loop in the transmitting circuit of FIG. 1;

FIG. 3 is a block diagram showing an example of a configuration of awireless communication apparatus using a high-frequency integratedcircuit (IC) using a polar loop method and a measuring system accordingto an embodiment of the present invention;

FIG. 4 is a block diagram showing an outline of a configuration of acircuit, which operates when an output power characteristic of an outputpower amplifier is measured;

FIG. 5 is a block diagram showing an outline of a configuration of acircuit which operates when an open gain characteristic of an amplitudecontrol loop is measured using a load, i.e., a load low-pass filter(LPF) 3 to reduce the number of poles to one in overall loops in thepolar-loop transmitting circuit according to an embodiment of thepresent invention;

FIG. 6 is a block diagram showing an outline of a configuration of acircuit which operates when an open gain characteristic of an amplitudecontrol loop is measured using a filter, i.e., an LPF 2 of a high degreein the polar-loop transmitting circuit according to an embodiment of thepresent invention;

FIG. 7 is a graph showing a frequency response characteristic inamplitude modulation when the amplitude control loop is in a closed loopstate;

FIG. 8A is a graph showing a relationship between an output controlvoltage VRAMP and gain of a variable gain amplifier circuit in apolar-loop transmitting circuit according to an embodiment of thepresent invention;

FIG. 8B is a graph showing a relationship between an output controlvoltage VRAMP and an output power of an output power amplifier in apolar-loop transmitting circuit according to an embodiment of thepresent invention;

FIG. 9 is a graph showing a gain characteristic of an open loop of anamplitude loop and a phase characteristic of the amplitude loop when aloop filter LPF 2 is used;

FIG. 10 is a circuit diagram showing a specific example of a variablegain amplifier circuit employed in an embodiment of the presentinvention;

FIG. 11 is a graph showing relationships between an output controlvoltage VRAMP and gain of a variable gain amplifier circuit (MVGA) on afeedback path and gain of a variable gain amplifier circuit (IVGA) on aforward path in a polar-loop transmitting circuit according to anembodiment of the present invention;

FIG. 12 is a graph showing relationships between an output controlvoltage VRAMP and a bias current of a variable gain amplifier circuit(MVGA) on a feedback path and a bias current of a variable gainamplifier circuit (IVGA) on a forward path in a polar-loop transmittingcircuit according to an embodiment of the present invention;

FIG. 13 is a circuit configuration diagram showing an example of aconfiguration of a gain control circuit employed in an embodiment of thepresent invention;

FIG. 14 is a configuration diagram showing an outline of a configurationof a bias current generator circuit constituting the gain controlcircuit of FIG. 13;

FIG. 15 is a graph showing a relationship between an output controlvoltage and a current of each current source and relationship between anoutput control voltage and a bias current obtained by combining thecurrents with each other;

FIG. 16 is a circuit diagram showing a specific example of the biascurrent generator circuit of FIG. 14;

FIG. 17 is a graph showing gain control sensitivity with respect to theoutput control voltage VRAMP of the output power amplifier;

FIG. 18 is a graph showing variation of gain of the variable gainamplifier circuit (IVGA) on the forward path in the polar-looptransmitting circuit according to an embodiment of the presentinvention;

FIG. 19 is a circuit configuration diagram showing another specificconfiguration example of the gain control circuit;

FIG. 20 is a circuit configuration diagram showing further anotherspecific configuration example of the gain control circuit;

FIG. 21 is a graph showing a characteristic of a bias current IIVGA ofthe variable gain amplifier circuit IVGA with respect to the outputcontrol signal VRAMP when gain of the amplifier is changed by a slopecontrol signal; and

FIG. 22 is a graph showing a characteristic of a bias current IIVGA ofthe variable gain amplifier circuit IVGA with respect to the outputcontrol signal VRAMP when gain of the amplifier is changed by an offsetcontrol signal.

DESCRIPTION OF THE INVENTION

FIG. 1 shows an outline of a configuration of an embodiment of atransmitting circuit of polar loop type according to the presentinvention. The configuration of FIG. 1 includes a high-frequencyintegrated circuit (IC) 100 to conduct GMSK modulation in a GSM systemor 8-PSK modulation in an EDGE system, a power module 200 including ahigh-frequency power amplifier circuit (to be abbreviated as a poweramplifier hereinbelow) 210 to conduct communication via an antenna ANTand a coupler 220 to detect transmission power, a baseband circuit 300which generates an I/Q signal according to transmission data (a basebandsignal), a control signal of the radio-frequency IC 100, and a biasvoltage VBIAS for the power amplifier 210 in the power module 200, atransmission oscillator TxVCO to generate a phase-modulated transmissionsignal (carrier wave), and a loop filter LPF1 to limit a bandwidth of aphase control loop.

The radio-frequency IC 100 is a semiconductor integrated circuit formedon one semiconductor chip. Although not shown in FIG. 1, there is formedon the chip of the radio-frequency IC 100, in addition to the circuitsfor transmission described above, a receiving circuit 190 (reference isto be made to FIG. 3) including a low-noise amplifier (LNA), a mixer(Rx-MIX) to directly convert a reception signal into a baseband signal,and a high-gain programmable gain amplifier (PGA). The radio-frequencyIC 100, the transmission oscillator TxVCO, the loop filter LPF, and thelike can be mounted on an insulating substrate such as a ceramicsubstrate into one module. The polar loop of the embodiment includes twocontrol loops, namely, a feedback loop for phase control (to be referredto as a phase loop hereinbelow) and a feedback loop for amplitudecontrol (to be referred to as a amplitude loop hereinbelow).

The radio-frequency IC 100 configuring the polar loop of the embodimentincludes a phase divider or demultiplexer circuit 110 which receives anintermediate-frequency oscillation signal φIF generated from anoscillator IF-VCO to generate signals apart 90° in phase from eachother, a quadrature modulator circuit 120 which conducts quadraturemodulation by mixing an I/Q signal from the baseband circuit 300 with adivided signal from the phase divider circuit 110, a mixer 131 whichmixes a feedback signal from the transmission oscillator TxVCO with anoscillation signal φRF signal from an RF-VCO to generate a signal havinga frequency of 80 MHz, a phase detector circuit 140 to detect a phasedifference between an output signal from the mixer 131 and an outputsignal from the quadrature modulator circuit 120, a mixer 132 to mix adetection signal from the coupler 220 to detect an output level from thepower amplifier with an oscillation signal φRF from the high-frequencyoscillator RF-VCO, a variable gain amplifier MVGA on feedback side toamplify an output from the mixer 132, an amplitude detector 150 tocompare the amplified signal with an output signal from the quadraturemodulator 120 to detect an amplitude difference, a loop filter LPF 2which generates a voltage corresponding to the output from the amplitudedetector 150 and which limits a frequency bandwidth of the amplitudeloop, a variable gain amplifier IVGA on forward side to amplify theoutput from the loop filter LPF2, a gain control circuit or controller160 to control gain of the variable gain amplifiers MVGA and IVGA, aregister 170 to store, for example, control information in the chip suchas an offset value and a slope value, which will be described later, andan operation mode; and sequencer 180 which outputs timing signals forcircuits in the chip according to values set to the register 170 tooperate the circuits in a specified order according to the operationmode. After IVGA, there are a VIC (voltage to current converter), acapacitor C1 and a level shifter LVS, followed by the switch SW1.

The coupler 220, the mixer 132, the amplifier MVGA, the amplitudedetector 150, the loop filter LPF2, the amplifier IVGA, and the poweramplifier 210 configure an amplitude loop. In the embodiment, the phasedetector 140, the loop filter LPF1, the oscillator TxVCO, the mixer 131,and the phase detector 140 configure a phase loop. Concretely, when aphase difference appears between the output signal from the quadraturemodulator 120 and the feedback signal from the mixer 131, a voltage toreduce the difference is fed to a frequency control terminal of thetransmitting oscillator TxVCO so that the phase of the feedback signalfrom the mixer 131 matches that of the output signal from the quadraturemodulator 120. The phase loop controls such that the phase of thefeedback signal from the mixer 131 is kept unchanged regardless ofvariation in the power source voltage and variation in temperature. Theamplitude of the signal from the oscillator TxVCO is fixed.

In the embodiment, the output from the variable gain amplifier MVGA isfed back to the phase detector 140 so that a path including the coupler220, the mixer 132, and the amplifier MVGA is used for both of theamplitude and phase loops. In the EDGE mode, the output from the poweramplifier 210 contains a phase-modulated component and anamplitude-modulated component. In GMSK mode, the feedback is taken fromthe TxVCO output. Therefore, either the output from the oscillator TxVCOor the output from the power amplifier 210 is available as the feedbacksignal to the phase detector 140, the signal including a phasecomponent. The loop with the feedback taken from the TxVO is called Subloop. The loop with the feedback taken from the power amplifier iscalled Main loop. However, at startup of transmission, the output fromthe power amplifier 210 is not at a specified level or is not ready forthe operation, the phase loop cannot be locked in EDGE mode. On theother hand, since the feedback path of the amplitude loop is required oressential in EDGE mode, the feedback path may provide feedback signalsto both the phase and amplitude detectors. This requires the amplitudeloop to be locked before the phase loop can be changed from Sub to Main.Then the feedback path associated with the phase loop can be turned off.This leads to an advantage that power consumption is reduced and thephase modulation can be conducted with high precision.

In GMSK mode, the amplitude loop does not require a very accuratecontrol of the amplitude signal. Therefore, a single pole is enough tocontrol the amplitude. This single loop filter guarantees stability ofthe loop and the open loop gain of the amplitude is designed to get agood compromise between noise suppression and amplitude loop bandwidth.The low open gain in GMSK mode is indicated by a broken line B in FIG.2. The corresponding gain loop bandwidth is 200 kHz in GMSK mode.However, to increase precision of the amplitude modulation, a wider loopbandwidth is favorable in EDGE mode. Therefore, to set the open loopfrequency bandwidth of the amplitude loop to a bandwidth of 1.8 MHz, theembodiment uses an amplitude loop filter implemented in two section. Thefirst section includes capacitors C2 and C3 and a resistor R3 connectedin series to the capacitor C3 and provides a low frequency pole, a zeroand a high frequency pole. The second section is comprised of thecapacitor C1 and provides a low frequency pole. The combination of thetwo sections results in the amplitude filter whose frequencycharacteristic is represented by solid line A.

However, in the amplitude loop including the loop filter LPF2 having twolow frequency poles, one zero and a high frequency pole. Stability isonly conditional. Stability is achieved at the condition that the phasemargin reaches a reasonable value at the frequency where the open loopgain is exactly equal to one.

In GMSK mode, the first section of the amplitude loop filter is replacedby a simple resistor so that the amplitude loop filter provides only onepole at low frequency and the amplitude loop remains stable. The loadLPF3 can also be used for calibrating the output power of thetransmitter. In GMSK mode, when the output from the power amplifier 210is to be controlled with a GMSK signal and/or when high-precisionamplitude control is not required, the load. LPF3 is preferred as itincreases the phase margin necessary to provide a very good loopstability. This leads to an efficient circuit configuration withoutincreasing the number of constituent components.

By disposing the load LPF3 and the switch SW2 and by controlling thegain of the amplifiers IVGA and MVGA of the amplitude loop according tothe output control voltage VRAMP from the baseband circuit 300 togenerate an output control voltage VAPC to the power module, the APCcircuit required for the GSM system of the prior art to detect theoutput level and to control the output from the power amplifier 210 canbe removed. Since amplitude modulation is not required when theamplitude loop is used in the GMSK modulation mode, the modulation loopis more stable in the GMSK mode than in the 8-PSK modulation mode.However, due to higher output power with GMSK signals, higher noiselevels are also output from the transmitter. Therefore, the loopbandwidth is desirably set to a value of 1.2 MHz, less than 1.8 MHz inEDGE mode and the amplitude loop bandwidth is at 200 kHz, less than 1.8MHz in the 8-PSK modulation mode. For this purpose, the ample loadresistor LPF3 used to provide only one pole in the overall loop is moresuitable as the amplitude loop filter than the two sections filter LPF2comprising two poles at low frequency, one zero and one pole at highfrequency. The radio-frequency IC 100 of the embodiment is configuredalso applicable to a GSM system where the power amplifier is controlleddirectly by the VRAMP signal. In such a case, the switch SW1 is set tosupply the signal from the VRAMP digital to analog converter directly tothe power module 200.

In the 8-PSK modulation mode, the output from the power amplifier 210 isdetected by the coupler 220 in the amplitude loop. The detected signalis converted by the mixer 132 into a signal of an intermediate-frequency(IF) bandwidth. The signal is amplified by the variable gain amplifierMVGA to a feedback signal SFB to be supplied to the amplitude detector150. In the detector 150, the feedback signal SFB is compared with atransmitting signal modulated by the quadrature modulator 120 toresultantly detect an amplitude difference. The difference is amplifiedby the variable gain amplifier IVGA to be applied as a control voltageVAPC to the output control terminal of the power amplifier 210 so as toachieve amplitude control. In the embodiment, the power amplifier 210includes, for example, a field-effect transistor (FET) with a drainterminal, a source terminal, and a gate terminal. The drain or sourceterminal is being applied with a voltage corresponding to the controlvoltage VAPC by a voltage control circuit (230 in FIG. 4) disposed inthe power module 200. The gate terminal is applied with an appropriatebias voltage VBIAS generated by a bias circuit, not shown.

Although not shown in FIG. 1, an attenuator ATT is disposed between thecoupler 220 and the mixer 132 to attenuate the output from the coupler220 to supply the attenuated signal to the mixer 132. Low-pass filtersMLPF1 and MLPF2 are respectively arranged between the mixer 132 and theamplifier MVGA and between the MVGA and the amplitude detector 150(reference is made to FIGS. 5 and 6).

In the embodiment, to set the sum of gain of variable gain amplifiersMVGA and IVGA to an almost fixed value, the respective gain values arecontrolled in mutually opposing directions by the gain control circuit160 according to the control voltage VRAMP from the baseband circuit300. In association therewith, the output voltage from the level shifterLVS or the control voltage VRAMP from the baseband circuit 300 can beselectively fed via the switch SW1 to the output control terminal of thepower amplifier 210 in the configuration. That is, in the embodiment,while the power amplifier 210 is controlled by the control voltage fromthe amplitude loop in the 8-PSK modulation mode. In the GMSK mode, thecontrol voltage VRAMP from the baseband circuit 300 can be supplied, inplace of the control voltage from the amplitude loop, directly to thepower amplifier 210 to control the output therefrom. The switch SW1operates under control of the sequencer 180 according to the settingstate of the register 170 set by the baseband circuit 300.

In the polar loop transmission circuit, a frequency responsecharacteristic of the system is determined according to the filter ofthe amplitude loop and gain of each component of the loop. To satisfyrequirements for modulation precision or error vector magnitude (EVM) ofa transmission waveform and the spectral re-growth, the magnitude loopdesirably has a higher frequency bandwidth. On the other hand, tosuppress noise in the receiving frequency bandwidth 20 MHz apart fromthe transmitting frequency, it is desired to reduce the frequencybandwidth of the magnitude loop. The inventors of the present inventionhave found that to satisfy the requirements of the EVM, the spectralre-growth, and the suppression of noise in the configuration of theembodiment, the open loop frequency bandwidth of the amplitude loop isdesirably set to a position about 1.8 MHz apart from the transmittingfrequency. To make the amplitude loop have an open loop frequencycharacteristic indicated by a solid line A in FIG. 2, the embodimentemploys as the loop filter LPF2 a two section filter which includescapacitors C2 and C3 and a resistor R3 connected in series to thecapacitor C3 and which has two poles and one zero.

However, since the frequency bandwidth of the loop actually varies dueto variation or dispersion of characteristics of constituent componentsof the amplitude loop in production, the requirements cannot besatisfied without prior calibration. Since root-mean-square (RMS) powerof the power amplifier is determined by the gain of the feedback path ofthe amplitude loop and the reference level, the output power from thepower amplifier 210 cannot be appropriately set when the gain variationsin the feedback path have not been calibrated out. More specifically,when the filter LPF2 including the capacitors C1, C2 and C3 and theresistor R3 is used, there exists a probability that the phase margin isnot sufficient to guarantee stability and that the loop oscillates. Toovercome the difficulty in the embodiment, the variation in gain of thefeedback path is measured as described below such that according toresults of the measurement, the gain values of the amplifiers MVGA andIVGA are calibrated to set the gain of the overall amplitude loop,namely, the frequency bandwidth of the amplitude loop to a value withina specified range in the vicinity of 1.8 MHz.

To keep the frequency bandwidth of the amplitude loop at a fixed value,it is necessary to keep the open loop gain at a fixed value. However, inthe operation to control the power amplifier output power by theamplitude loop, when the gain of the variable gain amplifier circuitMVGA on the feedback path changes, the gain of the amplitude loop alsovaries. This reduces the phase margin and hence the loop becomes lessstable. In the operation to control the power amplifier output power inthe embodiment, when the gain of the amplifier MVGA on the feedback pathincreases (decreases), the gain of the amplifier IVGA on the forwardpath is changed in the opposing direction, namely, is decreased(increased). As a result, the open loop gain can be kept at a fixedvalue and hence the frequency bandwidth of the amplitude loop is alsokept unchanged.

However, it is difficult to measure the entire system at once todetermine the variation in the frequency characteristic due to variationin characteristics of constituent components of the amplitude loop inproduction. According to the present invention, the amplitude loop isdivided into three sections respectively including the power amplifier,the feedback path, and the forward path, each of which needs to becalibrated.

The feedback path is a path ranging from the coupler 220 connected to anoutput port of the power amplifier to an input port of the amplitudedetector 150. The forward path is a path ranging from the input port ofthe amplitude detector 150 to an input port of the power amplifier.

As shown in FIG. 3, the radio-frequency IC 100, the power module 200,the baseband circuit 300, and a transmission/reception switch 400, and afilter 410 to remove unnecessary waves from the reception signal and thelike are mounted on a substrate to configure a portable telephoneterminal system 500. In this state, the measurement is carried out by ameasuring and arithmetic device 600.

Measurement 1

FIG. 4 shows circuits used in a first measurement. First, a probe 610extended from the measuring and arithmetic device 600 is brought intocontact with an output terminal of the power module 200 to measure anoutput voltage VRFOUT from the power amplifier 210 when the VRAMP signalapplied to the VAPC input is varied. Data thus measured is used tocorrect the variation in amplitude modulation gain of the poweramplifier 210. The output control voltage VAPC may be supplied from thebaseband circuit 300 or the measuring and arithmetic device 600.

Although not explained in conjunction with FIG. 1, the embodiment isconfigured to conduct, in addition to the GSM transmission, transmissionaccording to a digital cellular system (DCS) 1800. Therefore, in thesystem of the embodiment, the power module 200 includes power amplifiers210G and 210D which respectively amplify and output the transmissionsignals of the respective systems. Each of the amplifiers 210G and 210Dincludes a three-stage amplifier configured using a field-effecttransistor (FET) or the like. The bias voltage VBIAS is a voltage tosupply a bias point to a gate terminal of an amplifier FET of eachstage. The power module 200 includes a Vdd controller 230 whichgenerates and supplies a power source voltage Vdd according to theoutput control voltage VAPC, the voltage Vdd being fed to a drain of theamplifier FET of each stage.

In the first measurement, for example, the switch SW1 is set such thatthe feedback voltage from the amplitude loop is not fed to the powermodule 200, and the phase loop is set to an effective state. In thisstate, an oscillation signal φTX from the transmitting oscillator TxVCOis fed to an input terminal of the power amplifier 210G or 210D and thebias voltage VBIAS is applied as above. By directly controlling thepower module 200 by the output control voltage VPAC (VRAMP), an outputvoltage VRFOUT from each of the power amplifiers 210G and 210D ismeasured. The measured values are calculated to obtain an outputcharacteristic of each of the power amplifiers 210G and 210D withrespect to the control voltage VAPC.

Specifically, according to the measured data, a function (an expression)indicating a relationship between the output voltage VREF_(out) from thepower amplifier and the output control voltage VAPC is obtained. Bydifferentiating the function, a first differential function α₁ and asecond differential function α₂ are obtained. The first differentiationα₁ indicates whether or not the gain dVRF_(OUT)/dVAPC of the poweramplifier linearly changes with respect to the output control voltageVAPC. According to the measured results, a control table to change theoutput power POUT from the power amplifier with respect to the outputcontrol voltage VAPC can be produced. By storing the control table inthe nonvolatile memory 310 of the baseband circuit 300 and by outputtingthe output control voltage VRAMP during the transmission of data, it ispossible to control the power amplifier in the direct mode.

According to the second differential function α₂, a slope parameter,which will be described later, is obtained for each power amplifier GSMand DCS. The second differentiation, α₂, indicates whether the rate ofchange of the gain is positive or negative, as if the gain of the poweramplifier increases or decreases with VAPC. The slope parameters arestored in the nonvolatile memory 310 of the baseband circuit 300. Datato adjust the gain values of the amplifiers MVGA and IVGA can beobtained according to the slope parameters. By supplying the data to theradio-frequency IC such that the IC outputs a control voltage VAPC tocorrect the characteristic of the power amplifier. This leads to adesired linear operation of the power amplifier 210.

Measurement 2

FIG. 5 shows an outline of the second measurement. The measurement isconducted to gather data to calibrate gain variation in the feedbackpath of the amplitude loop.

In consideration of stability of the amplitude loop, the gainmeasurement is conducted using the load LPF3 including a resistor RT1having a frequency characteristic indicated by a broken line B in FIG.2. The resistor RT1 has a resistance value to set the open loopfrequency bandwidth of the amplitude loop including the load LPF3 toabout 200 kiloherz (kHz). The amplitude loop including the load LPF3 hasonly one pole and hence the phase margin does not decrease below 90°.This guarantees stability of the loop. The system of the secondmeasurement operation with a type I amplitude loop in which integrationappears once in the open loop transfer function or one pole exists at alow-frequency. However, provided the stability is guaranteed by low gainvariation in the loop, it is possible to use type II in whichintegration appears twice in the open loop transfer function or twopoles exist at low-frequency.

In the second measurement, the oscillation signal φTX is applied fromthe transmitting oscillator TxVCO to the input terminal of the poweramplifier 210 and the bias voltage VBIAS is also applied as shown inFIG. 5, and the output control voltage VRAMP is applied to the gaincontroller 160 to control the gain values of the variable gainamplifiers MVGA and IVGA. While applying a reference signal SREF notmodulated to the amplitude detector 150, the amplitude loop is operatedin a closed loop to measure the output voltage VRFOUT from the poweramplifier 210 in this state. The output control voltage VRAMP to be fedto the gain controller 160 may be supplied from the baseband circuit 300or the measuring and arithmetic device 600.

A power amplifier output characteristic Pout [dBm] with respect to theoutput control voltage VRAMP to set a gain of the variable gainamplifier MVGA on the feedback path is then measured. The measured datais calculated to obtain an output control voltage VRAMP necessary toobtain a desired amplifier output to produce a control table. Thecontrol table is stored in the nonvolatile memory 310 in the basebandcircuit 300. When the load LPF 3 is used to operate the loop fortransmission, the data in the control table is set from the basebandcircuit 300 to the register 170 in the radio-frequency IC 100 for actualcontrol. The data obtained in the second measurement is also used todetermine the output control voltage VRAMP supplied from the basebandcircuit 300 to the radio-frequency IC 100.

Measurement 3

FIG. 3 shows an outline of the third measurement. The measurement isconducted to gather data to calibrate gain variation in the overallamplitude loop.

In the third measurement, the switch SW2 selects, as the loop filter,the filter LPF2 including the capacitors C1, C2 and C3 and the resistorR3 to set the magnitude loop to a loop having a frequency characteristicindicated by a solid line A in FIG. 2. The gain measurement is conductedin this state. Therefore, the amplitude loop including the loop filterLPF2 has an open loop frequency bandwidth of about 1.8 MHz. The thirdmeasurement is conducted after the amplitude loop stability is increasedby conducting the second measurement (to prevent oscillation).

In the third measurement, the oscillation signal φTX is applied from thetransmitting oscillator TxVCO to the input terminal of the poweramplifier 210 and the bias voltage VBIAS is also applied as shown inFIG. 6, and the output control voltage VRAMP is applied to the gaincontroller 160 to control the gain values of the variable gainamplifiers MVGA and IVGA. While applying an amplitude-modulatedreference signal to the amplitude detector 150, the amplitude loop isoperated in a closed loop (type II) to measure the output voltage VRFOUTfrom the power amplifier 210 in this state. The output control voltageVRAMP to be fed to the gain controller 160 may be supplied from thebaseband circuit 300 or the measuring and arithmetic device 600.

In the third measurement, a current pulse from the current pulsegenerator CPG is applied to the input terminal of the amplifier IVGA tomeasure the side band frequency levels at the output of the poweramplifier 210 in this state. As a result, the loop gain is alsocalculated for a frequency (receiving frequency) which is apart, forexample, about 2 MHz from the frequency of the carrier signal (TxVCO).The current pulse generator CPG can be configured using an amplifier anda charge pump. The circuit is beforehand incorporated in the chip.However, the system may be configured so that a specified current pulsecan be externally supplied to the input terminal of the amplifier IVGA.When the current pulse generator CPG is incorporated in the chip, thesystem may be configured such that a clock signal generated from ahigh-precision oscillator circuit such as a crystal oscillator isexternally supplied to the system. The current pulse generator CPG thendivides the clock signal to generate a current pulse having a specifiedfrequency.

FIG. 7 shows a frequency response characteristic when the amplitudemodulation is conducted in the closed-loop state. In the amplitudemodulation, the amplitude of a modulated signal is kept unchanged (themodulation index or radio deviation is fixed), and the operation isconducted with at least two amplitude modulating frequencies to varyonly the side-band frequency of the amplitude-modulated signal.Specifically, a frequency contained in a passing band of the frequencycharacteristic of the amplitude loop, for example, a frequency about 100kHz from the transmitting frequency Fc) is selected as a firstmodulating frequency Fm1. A frequency contained in an attenuation bandof the frequency characteristic of the amplitude loop, for example, afrequency about 2 MHz from the transmitting frequency Fc) is selected asa second modulating frequency Fm2.

According to the measured power amplifier output (or the antennaoutput), a frequency spectrum of the amplitude-modulated signal isanalyzed to obtain a power level to frequency characteristic of theside-band component. In FIG. 7, a solid line AA is an example of anideal characteristic and a broken line BB is an example of a measuredcharacteristic. The abscissa indicates the frequency in logarithm inFIG. 7. In this case, the broken line BB indicates that the measuredfrequency characteristic is higher than the ideal frequencycharacteristic. In the neighborhood of a frequency (a unity gainfrequency) at which the gain is “1” in the open loop characteristic(type II), the closed loop gain shows a small peaking. Therefore, amodulating frequency above this frequency is chosen so that anattenuation can be measured.

The frequency characteristic resulting from the third measurement iscalculated and compared to the desired characteristic. From thiscomparison can be calculated a relative difference in the amplitude loopgain. This difference is used to act the open loop gain so that the openloop frequency bandwidth satisfies the condition of about 1.8 MHz. Thereis obtained a gain offset value to be supplied to the variable gainamplifier IVGA on the forward path so that the frequency bandwidthsatisfies the condition of about 1.8 MHz. The gain offset value isstored as a control data in the nonvolatile memory 310 of the basebandcircuit 300. When the loop is operated using the filter LPF2 to conducttransmission in the 8-PSK modulation mode, the data in the control tableis set from the baseband circuit 300 to the register 170 in theradio-frequency IC 100 for actual control.

The gain variations of the power amplifier 210 and the amplitude loopare obtained by conducting calculations using data items obtainedthrough the first, second, and third measurement. Calibration orcorrection values (offset values and slope of the open loop gain values)necessary to calibrate the variations are then calculated to be storedin the nonvolatile memory 310 of the baseband circuit 300. At startup oftransmission of the modulated signal, the values are sent to and are setto the register 170 of the radio-frequency IC 100. The offset values setto the register 170 is supplied to the variable gain amplifier IVGA onthe forward path to cancel the variations of the differentialcharacteristic dVR_(OUT)/dVAPC of the power amplifier, the variations ofthe sum of the gain of the feedback path and the variations of the gainof the forward path, to set the open loop frequency bandwidth to about1.8 MHz. The slope values are supplied to the variable gain amplifierIVGA on the forward path to compensate for the second differentialfunction α2 of the input/output characteristic of the power amplifier.As a result, the variation in the characteristic of the power amplifierand the variation in the frequency bandwidth of the amplitude loop dueto the variation in characteristics of constituent components inproduction can be reduced.

Next, description will be given of gain control for the variable gainamplifier IVGA on the forward path and the variable gain amplifier MVGAon the feedback path.

To keep the amplitude loop frequency bandwidth in a fixed band, it isnecessary to keep the open loop gain at a fixed value as describedabove. However, in an operation to control the power amplifier outputpower by the amplitude loop, when the gain of the amplifier MVGA on thefeedback path changes, the gain of the amplitude loop varies and thefrequency bandwidth changes resulting in low phase margin. This lowersstability of the loop. To cope with the difficulty in the embodiment, inthe operation to control the output power of the power amplifier, whenthe gain of the amplifier MVGA on the feedback path increases, the gainof the amplifier IVGA on the forward path is decreased. Conversely, whenthe gain of the amplifier MVGA on the feedback path decreases, the gainof the amplifier IVGA on the forward path is increased. This keeps theopen loop gain at a fixed value, and hence the frequency bandwidth ofthe amplitude loop is kept in a fixed band.

In a portable telephone terminal for the EDGE or GSM system, the poweris controlled such that the output power P of the power amplifier isincreased or decreased to a predetermined value within a fixed period oftime. In the polar loop, the power control operation is conducted bycontrolling the gain of the amplifier MVGA. Specifically, since thefeedback signal of the amplitude loop decreases when the gain of theamplifier MVGA is decreased, in reaction, the power amplifier iscontrolled to increase the gain GPA (POUT/PIN) for the matching thefeedback signal with the reference signal from the modulation circuit.Therefore, the output power POUT is increased. When it is desired toreduce the output power POUT, the gain of the amplifier MVGA is simplyincreased. In the embodiment, the gain of the amplifier MVGA iscontrolled by the control voltage VRAMP from the baseband circuit 300.

In the embodiment, the rate of decrease or increase in the gain GMVGA ofthe variable gain amplifier MVGA and that of increase or decrease in thegain GPA of the power amplifier 210 are fixed in any situation.Therefore, the gain variation of the amplifier MVGA with respect to thecontrol voltage VRAMP is indicated by a straight line, i.e., a solidline GPA drawn from an upper left point to a lower right point in FIG.8A. The RF gain variation of the power amplifier 210 with respect to thecontrol voltage VRAMP is indicated by a straight line, i.e., a solidline GPA drawn from a lower left point to an upper right point in FIG.8A. The output power POUT of the power amplifier 210 expressed in dBm,linearly increases with respect to the control voltage VRAMP expressedin V as shown in FIG. 8B. The operation to linearly control the outputpower POUT of the power amplifier 210 by the control voltage VRAMP in dBunit is effective to operate the amplitude loop in a stable state.

On the other hand, the reference signal SREF from the modulation circuitis a signal modulated in the 8-PSK modulation and the amplitudecomponent of the signal is changed. However, the amplitude component ofthe output power POUT from the power amplifier 210 is controlled tomatch that of the reference signal SREF by the action of the amplitudecontrol loop. The output power POUT of the power amplifier 210 is keptat a specified value by the power control operation described above.That is, according to the polar loop, when keeping VRAMP constant, thegain of the MVGA is fixed and the output power of the power amplifier isexactly following the variations of the reference signal with thefeedback gain as a fixed ratio.

However, to operate the amplitude loop in a stable state, variations inthe open loop gain of the amplitude loop must be possibly reduced to theminimum. FIG. 9 shows a frequency characteristic of the open loop of theamplitude loop using the loop filter LPF2. While (A) of FIG. 9 shows again characteristic of the amplitude loop, (B) of FIG. 9 shows a phasecharacteristic of the amplitude loop. PM0 to PM2 indicate phase margins.Decrease in the phase margin deteriorates stability of the amplitudeloop. This is a problem to be solved. The open loop gain GAMOP of theamplitude loop increases or decreases in proportion to the variation inthe gain GMVGA of the amplifier MVGA. Since the phase of the loop doesnot change in this case, the phase margin is reduced to PM1 or PM2relative to the phase margin PM0 appearing when the gain of theamplifier MVGA is set at the optimum value.

In the embodiment, the problem is solved by controlling the amplifiersMGVA and IVGA so that the sum (GIVGA+GMVGA) of the gain of the amplifierIVGA on the forward path and that of the amplifier MVGA on the feedbackpath is fixed. In other words, the relationships between the controlvoltage VRAMP and the gain GIVGA and the gain GMVGA are drawnrespectively as a straight line extending upward to the right and astraight line extending downward to the right as shown in FIG. 11.

In the embodiment, as shown in FIG. 1, the gain controller 160 generatesbias currents IMVGA and IIVGA according to the control voltage VRAMP,and the gain GMVGA and the gain GIVGA respectively of the amplifiersMVGA and IVGA are controlled respectively by the bias currents IMVGA andIIVGA from the gain controller 160. Assume that each of the amplifiersMVGA and IVGA includes a general differential amplifier including abipolar transistor. The gain GAMP of the differential amplifier isexpressed asGAMP=20 log₁₀(VOUT/VIN)=20 log₁₀(RL·IEE/2VT)  (1)In equation (1), IEE is a bias current of the differential amplifier, RLis a load resistor, and VT is a thermoelectric voltage (KT/q).

The gain of the amplifier is proportional to the bias current IEE asindicated by equation (1). Therefore, to linearly change the gain GMVGAand the gain GIVGA in dB respectively of the amplifiers MVGA and IVGAwith respect to VRAMP, the bias currents IMVGA and IIVGA must be variedalong an exponential function of the control voltage VRAMP. The biascurrent IIVGA of the amplifier IVGA is expressed asIIVGA=IEE·exp(log_(e)10·VRAMP).

The gain controller 160 of FIG. 1 includes, as shown in FIG. 13, currentsource circuits CS1 and CS2 to respectively generate exponentiallychanging bias currents IMVGA and IIVGA and single differentialamplifiers SDA1 and SDA2 respectively drive the current source circuitsCS1 and CS2. The control voltage VRAMP is fed to an inverse inputterminal of the amplifier SDA1 and the reference voltage VREF is appliedto a non-inverse input terminal thereof. Conversely, the control voltageVRAMP is fed to a non-inverse input terminal of the amplifier SDA2 andthe reference voltage VREF is applied to an inverse input terminalthereof. The target is that, the bias current IIVGA of the amplifierIVGA and the bias current IMVGA of the amplifier MVGA change withrespect to the control voltage VRAMP along a curved line of anexponential function shown in FIG. 12.

When the bias currents IMVGA and IIVGA are fed respectively to theamplifiers MVGA and IVGA, the gain GIVGA of IVGA and the gain GMVGA ofMVGA linearly change as shown in FIG. 11. Therefore, the sum of the gainGIVGA+GMVGA if kept fixed. Consequently, even when the gain of theamplifier MVGA is changed to control the output power POUT of the poweramplifier 210, the open loop characteristic of the amplitude loop is notchanged and hence the phase margin is not reduced.

Description will now be given of a concrete circuit example of the gaincontrol circuit 160 to generate the exponentially changing bias currentsIMVGA and IIVGA. FIG. 14 shows an outline of the current source circuitCS2 to generate the bias current IIVGA to be fed to the amplifier IVGA.The current source circuit CS2 of the embodiment includes a plurality ofvariable current sources VC1, VC2, . . . , VCn having mutually differentcurrent values and start levels. The variable current sources VC1, VC2,. . . , VCn are controlled by the input control voltage VRAMP and mixesthe currents therefrom with each other to produce a bias current. Theobtained current exponentially varies with respect to the controlvoltage VRAMP.

Specifically, the variable current sources VC1, VC2, . . . , VCn areconfigured to respectively have voltage-current characteristics shown in(A) of FIG. 15. As can be seen from (A) of FIG. 15, the currentslinearly changed in a range of ±ΔV centered respectively on a referencevoltage VR1, VR2, . . . , VRn. A current saturation level of eachcurrent source is substantially equal to a current start level of itssubsequent current source. A gradient or slope of the straight line,namely, a current change ratio sequentially becomes greater in an orderof the current sources I1, I2, . . . , In. In the current source circuitCS1 of the embodiment, the currents I1, I2, . . . , In from the currentsources VC1, VC2, . . . , VCn are mixed with each other to produce thesum of the current values of the currents, and a current equal in thecurrent value to the obtained current is fed as the bias current IIVGAto the amplifier IVGA. The current approximates an exponential variationwith respect to the control voltage VRAMP. Consequently, the gain of theamplifier IVGA expressed in dB linearly changes with respect to thecontrol voltage VRAMP.

In (B) of FIG. 15, a solid line shows how the bias current IIVGA changeswith respect to the control voltage VRAMP. As can be seen from the graphof (B), the bias current IIVGA changes like a broken-line graph. A firstline segment A1 is a current I1 of the current source VC1, a subsequentline segment A2 is the sum of the currents I1 and I2 of the currentsources VC1 and VC2, a further subsequent line segment A3 is the sum ofthe currents I1, I2, and I3 of the current sources VC1, VC2, and VC3,and a last line segment An is the sum of the currents I1, I2, . . . , Inof the current sources VC1 to VCn. In the current source circuit CS2 ofthe embodiment, the current values I1, I2, . . . , In respectively ofthe current sources VC1 to VCn are set such that the broken line of (B)of FIG. 15 approximates to an exponential curve. The current sourcecircuit CS2 to generate the bias current IMVGA of the variable gainamplifier MVGA is configured such that the mixed currents obtained bymixing currents from a plurality of variable current sources with eachother form a line which exponentially decreases as indicated by thebroken line in (B) of FIG. 15.

FIG. 16 shows a concrete example of a circuit configuration of the biascurrent. The variable current sources VC1, VC2, . . . , VCn respectivelyinclude bipolar transistors Q11, Q21, . . . , and Qn1 of which baseterminals are applied with associated reference voltages VR1, VR2, . . ., and VRn; and transistors Q12, Q22, . . . , Qn2 respectively associatedwith the transistors Q11, Q21, . . . , and Qn1. The configurationfurther include resistors, R11 and R12, R21 and R22, . . . , Rn1 andRn2; and constant current sources IE1, IE2, . . . , IEn respectivelyassociated with the transistors Q12, Q22, . . . , Qn2. Each associatedpair of the transistors, for example, the pair of Q11 and Q12 isconnected as follows. Emitters of Q11 and Q12 are connected respectivelyvia the resistors R11 and R12 to the current source IE1. The other pairsof the transistors are also connected via the associated resistors tothe associated current sources as shown in FIG. 16. In the pair of thetransistors including a first transistor and a second transistor, acollector terminal of the first transistor is connected to a powersource voltage Vcc and the second transistor is commonly connected tothe other second transistors of the other transistor pairs. As a result,collector currents I1, I2, . . . , In respectively of Q12, Q22, Qn2 aremixed with each other to produce a bias current Iout.

To generate base voltages VR1, VR2, . . . , VRn respectively of thetransistors Q11, Q21, . . . , and Qn1 and base voltages VB1, VB2, . . ., VBn respectively of the transistors Q12, Q22, . . . , Qn2 according tothe control voltage VRAMP to control the output level of the linearamplifier 10, a resistance type potential divider circuit 22 isarranged. To supply an offset current Ioff, there is disposed, inaddition to the current sources VC1, VC2, . . . , VCn, a current sourceCoff including transistors Q01 and Q02, resistors R01 and R02, aconstant current transistor Qc0, and an emitter resistor Re0. Thecurrent source Coff is arranged to supply a minimum bias current to alinear amplifier 10 even when the control voltage VRAMP is zero volt.

The constant current sources IE1, IE2, . . . , and IEn of the variablecurrent sources VC1, VC2, . . . , VCn include bipolar transistors Qcq,Qc2, . . . , Qcn and emitter resistors Re1, Re2, . . . , Ren,respectively. Bases of the transistors Qcq, Qc2, . . . , Qcn are appliedwith a voltage substantially equal to a base voltage of a transistorconnected to the transistors in a current mirror configuration. Sincethe constant current source IEi of each variable current source VCi(i=1, 2, . . . , n) includes a bipolar transistor Qci and an emitterresistor Rei, the current variation due to the variation in thebase-emitter voltage VBE of the transistor becomes smaller when comparedwith the current source which only uses transistors and which does notuse the emitter resistors.

Since the reference current IREF flows through the transistor Qcr in theconfiguration, currents Ie1, Ie2, . . . , Ien, and Ioff are suppliedrespectively to the transistors Qc1, Qc2, . . . , Qcn and Qco inproportion to the reference current IREF. The current ratios aredetermined according to size ratios respectively between the size of thetransistor Qcr (particularly, the emitter) and the transistors Qc1, Qc2,. . . , Qcn and Qco and ratios between resistance values of theresistors Re1, Re2, . . . , Ren, respectively. The currents Ie1, Ie2, .. . , Ien respectively flowing through the transistors Qc1, Qc2, . . . ,and Qcn are saturation currents respectively of the variable currentsources VC1, VC2, . . . , VCn of the current source circuit CS2 shown inFIG. 14. The resistance values of the resistors R01 and R02, R11 andR12, . . . , Rn1 and Rn2 determine the current variation ratio(gradients respectively of the line segments A1, A2, . . . , An shown in(B) of FIG. 15). For each of the variable current sources VC1, VC2, . .. , VCn, a current variation range ±ΔV is determined by the base voltagedifference between the paired transistors.

That is, to set the base voltage difference between the pairedtransistors, the resistance type potential divider circuit 22 generatesthe base voltages VR1, VR2, . . . , VRn for the transistors Q11, Q21, .. . , Qn1 and the base voltages VB1, VB2, . . . , VBn for thetransistors Q12, Q22, . . . , Qn2. In the potential divider 22, theresistance ratios are set such that crossing voltages between thevoltages VR1, VR2, . . . , VRn and the voltages VB1, VB2, . . . , VBnchanging in association with the control voltage VRAMP become centralvoltages respectively of current waveforms I1, I2, . . . , In.

In the gain controller 160 of the embodiment, the resistance valuesrespectively of the resistors R01 and R02, R11 and R12, . . . , and Rn1and Rn2 determine the current change ratios of the respective variablecurrent sources VC1, VC2, . . . , VCn. Therefore, the resistance ratiosare almost fixed even the resistance values change, which leads to anadvantage that the exponential curve of the bias current IIVGA obtainedas the resultant current shown in (B) of FIG. 15 can be almost keptunchanged.

Next, description will be given of calibration or correction of thevariation in the open loop gain of the amplitude loop. The variation iscaused, for example, by the gain variations of circuits on the amplitudeloop. The variations are due to the variation in characteristics ofconstituent components in production and must be corrected. For example,assume that the characteristic of the output power POUT of the poweramplifier 210 with respect to the output control voltage VRAMP is gaincontrol sensitivity APA. Then, the sensitivity APA of the poweramplifier 210 is desirably fixed in the embodiment. FIG. 17 shows acharacteristic example of the gain control sensitivity APA expressed indB of the power amplifier 210 to the output control voltage VRAMP.

The gain control sensitivity APA of the power amplifier 210 is favorablyfixed regardless of the control voltage VRAMP as indicated by a straightline APA0 in FIG. 17. However, the characteristic line possibly inclinesas lines APA1 and APA2 depending on a power amplifier used in theconfiguration. To overcome the difficulty, there is known a method tocorrect the variation by changing the gain control sensitivity of thevariable gain amplifier IVGA. FIG. 18 shows the characteristic obtainedby changing the gain control sensitivity of the variable gain amplifierIVGA. In FIG. 18, a strait line GIVGA0 is a target gain characteristic.When the control sensitivity is reduced relative to that correspondingto the line GIVGA0, there is obtained a straight line GIVGA1 havingsmaller inclination. Conversely, when the control sensitivity isincreased, there is obtained a straight line GIVGA2 having largerinclination.

In a specific correction method, when the gain control sensitivity APAof the power amplifier 210 has, for example, positive inclination likethe characteristic line APA1 shown in FIG. 17, the inclination of thegain characteristic of the variable gain amplifier IVGA is reduced likethe straight line GIVGA1. As a result, the sum (APA+GMVGA+GIVGA) of thegain APA of the power amplifier 210, the gain GMVGA of the amplifierMVGA, and the gain of the amplifier IVGA is kept fixed with respect tothe output control voltage VRAMP. The control characteristic of the gainGMVGA of the amplifier MVGA is fixed by design and is not programmable.Conversely, when the gain APA of the power amplifier 210 has negativeinclination like the characteristic line GAP2 shown in FIG. 17, thecorrection is conducted to increase the inclination of the gaincharacteristic of the amplifier IVGA as indicated by the straight lineGIVGA2. The correction of gain control sensitivity is called “slopecorrection” in the present specification.

Now let's describe how the offset is calculated when the gain APA of thepower amplifier 210 and gains of other circuits simply increase ordecrease depending on the production margins. Description will be givenof a case in which the gain control sensitivity APA of the poweramplifier 210 varies as indicated by broken lines APA3 and APA4 in FIG.17 with respect to the straight line APA0 as a target characteristic. InFIG. 17, the straight lines APA3 and APA4 show characteristicsrespectively when the gain control sensitivity APA of the poweramplifier 210 increases and decreases. To correct the variations, thecontrol characteristic of the gain GIVGA of the variable gain amplifierIVGA is shifted in an appropriate manner. In FIG. 18, a characteristicindicated as GIVGA3 is obtained when the control characteristic of thegain GIVGA of the amplifier IVGA is shifted to reduce the gain, and acharacteristic indicated as GIVGA4 is obtained when the controlcharacteristic of the gain GIVGA of the amplifier IVGA is shifted toincrease the gain.

When the gain APA of the power amplifier 210 increases as APA3 in FIG.17, the control characteristic of the gain GIVGA of the amplifier IVGAis generally shifted to reduce the gain as the straight line GIVGA3 inFIG. 18. Conversely, when the sensitivity APA of the power amplifier 210decreases as APA4 in FIG. 17, the control characteristic of the gainGIVGA of the amplifier IVGA is generally shifted to increase the gain asthe straight line GIVGA4 in FIG. 18. Even when gains of the circuitsvary due to production margins, the sum (APA+GMVGA+GIVGA) of the gainAPA of the power amplifier 210, the gain GMVGA of the amplifier MVGA,and the gain of the amplifier IVGA can be kept fixed with respect to theoutput control voltage VRAMP. The gain correction is called “offsetcorrection” in this specification.

Description will now be given of an embodiment of a circuit for thecorrection. FIG. 19 shows a specific example of the gain control circuit160 to conduct the slope correction and the offset correction. Thecircuit 160 of the embodiment is configured such that gain of a singledifferential amplifier SDA2 can be corrected by a slope control signalSLOPE for the slope correction. In the gain controller 160, when thegain of the amplifier SDA2 is set to a higher value by the slope controlsignal SLoPE, the change ratio of the bias current IIVGA becomes higher.That is, the inclination of the gain GIVGA of the amplifier IVGA can beincreased. Conversely, the inclination of the gain GIVGA of theamplifier IVGA can be decreased by setting the gain of the amplifierSDA2 to a lower value.

FIG. 21 shows a characteristic of the bias current IIVGA of theamplifier IVGA with respect to the output control signal VRAMP when thegain of the amplifier SDA2 is changed by the slope control signal SLOPE.In FIG. 21, a characteristic curve H1 is obtained when the gain of theamplifier SDA2 is increased. The change ratio of IICGA with respect toVRAMP is increased, and the characteristic curve is compressed in adirection of the abscissa centered on the reference voltage VREF.Conversely, a characteristic curve H2 is obtained when the gain of theamplifier SDA2 is reduced. The change ratio of IICGA with respect toVRAMP is reduced, and the characteristic curve is expanded in thedirection of the abscissa. Therefore, when the gain of the amplifierSDA2 is increased, the inclination of the gain GIVGA of the amplifierIVGA is increased as GIVGA2 in FIG. 18. When the gain of the amplifierSDA2 is reduced, the inclination of the gain GIVGA of the amplifier IVGAis reduced as GIVGA1 in FIG. 18.

In the embodiment of FIG. 19, the variable gain amplifier IVGA includesa first amplifier AMP1 and a second amplifier AMP2. The first amplifierAMP1 has a function substantially equal to that of the variable gainamplifier IVGA of the embodiment shown in FIG. 13. Gain of the secondamplifier AMP2 is changed by an offset control signal OFST. In theembodiment, the gain GIVGA of the amplifier IVGA can be controlled asGIVGA3 and GIVGA4 by changing the gain of the second amplifier AMP2. Asa result, the sum (APA+GMVGA+GIVGA) of the gain APA of the poweramplifier 210, the gain GMVGA of the amplifier MVGA, and the gain of theamplifier IVGA can be kept fixed. In the configuration of the embodimentshown in FIG. 19, the gain of the first amplifier AMP1 is controlled bythe current IIVGA from the gain controller 160 and the gain of thesecond amplifier AMP2 is controlled by the offset control signal OFST.However, the current IIVGA and the offset signal OFST may be exchangedin the configuration to obtain a similar advantage.

In another method of offset correction, a level shift circuit LSF isarranged as shown in FIG. 20 such that a reference voltage VREF suppliedto the single differential amplifier SDA2 is shifted by a specifiedamount of voltage. The level shift circuit LSF is a circuit which adds afixed voltage VSHIFT to the received voltage to produce a voltage as aresult of the addition. The shift voltage VSHIFT is controlled by theoffset signal OFST. FIG. 22 shows operation of the embodiment. When theshift voltage VSHIFT is increased by the level shift circuit LSF, thecharacteristic curve of the bias current IIVGA of the amplifier IVGA isshifted to the right as indicated by H3. Conversely, when the shiftvoltage VSHIFT is reduced, the characteristic curve of the bias currentIIVGA is shifted to the left as indicated by H4.

When the shift voltage VSHIFT is increased, the gain characteristiccurve of the amplifier IVGA is generally shifted downward as indicted byGIVGA3 in FIG. 18. Conversely, when the shift voltage VSHIFT is reduced,the gain characteristic curve of the amplifier IVGA is generally shiftedupward as indicted by GIVGA4 in FIG. 18. Resultantly, the sum(APA+GMVGA+GIVGA) of the gain APA of the power amplifier 210, the gainGMVGA of the amplifier MVGA, and the gain of the amplifier IVGA can beset to a target value. In the embodiment of FIG. 20, the level shiftcircuit LSF is arranged on the input side of the reference voltage VREFof the differential amplifier SDA2. However, the level shift circuit LSFmay be arranged on the input side of the gain control signal VRAMP ofthe differential amplifier SDA2. However, the relationship between theshift voltage VSHIFT and the gain GIVGA of the amplifier IVGA isreversed in this case. That is, when the shift voltage VSHIFT isincreased, the characteristic curve of the bias current IIVGA of theamplifier IVGA is shifted to the left. Conversely, when the shiftvoltage VSHIFT is reduced, the characteristic curve of the bias currentIIVGA is shifted to the right.

In the polar loop, the phase and the amplitude of the power amplifiercan be appropriately controlled by the combination effect of the phaseloop and the amplitude loop. Therefore, the polar loop is suitablyapplicable to a dual mode transmitting circuit coping with the GSM andEDGE systems. This is because only the phase component has informationto be transmitted in the GSM system adopting the GSM modulation and theamplitude component also has such information to increase the transferrate in the EDGE system. In the transmitting circuit using only the GSMsystem of the prior art, the power amplifier is controlled to obtain afixed output amplitude. The amplitude loop with a type I amplitude loopcan be used to control the amplitude of the GMSK signal and make sure itdoes not change during transmission. In the polar loop, the feedbacksignal from the output of the power amplifier is compared with theoutput from the modulation circuit. Therefore, the power amplifieroutput (a mean value of output power of the power amplifier) can becontrolled without adversely influencing the amplitude-modulatedcomponent of the EDGE system. Consequently, the configuration can bothfor the GMSK system and the EDGE system using the amplitude-modulatedcomponent.

However, in both of the GMSK and EDGE system, the power amplifier outputmust has lower sensitivity with respect to variation in temperature andvariations in constituent components. The standards of the GSM systemstipulate that power at an antenna end port during the rump-up period,the rump-down period, and data transmitting period must be within aspecified time mask in any situation. To conduct such control of theoutput power in the polar loop, it is required that characteristics ofcircuits in the loop are reasonably stable. It is also required that thevariable gain amplifiers MVGA and IVGA have a wide variable gain range(about 50 dB) and the variations are suppressed over the complete range.Therefore, the control operation is quite difficult. If the variationsare beyond the allowable range, there can also be considered to employ amethod in which the baseband circuit acquires information of thevariations to control the gain values of the amplifiers MVGA and IVGA toresultantly correct the variations. However, in this method, theproduction cost of the baseband circuit disadvantageously soars. Whenthe gain of the variable gain amplifiers is nonlinear with respect tothe control signal, the load imposed on the baseband circuit is alsoincreased and hence the production cost thereof soars. Therefore, it isdesired that the gain is linear with respect to the control signal.

Consequently, according to the embodiment, there can be implemented avariable gain amplifier with a wide variable gain range which has lowsensitivity to variations in the power supply, temperature, andconstituent components and high linearity in gain control. This lowersthe load imposed on the baseband circuit and hence the production costthereof can be reduced.

The present invention has been described in detail using embodiments.However, the invention is not limited to the embodiments, but can bemodified in various fashions without departing from the spirit and scopethereof.

For example, in the embodiments, the radio-frequency IC 100 includes theregister 170 to set data to correct gain characteristics of the variablegain amplifiers MVGA and IVGA. Data to correct gain characteristics ofthe variable gain amplifiers MVGA and IVGA is beforehand stored in thenonvolatile memory 310 of the baseband circuit 300. At initiation ofoperation, the data is fed from the baseband circuit 300 to theradio-frequency IC 100 to be set to the register 170. However, it isalso possible that the radio-frequency IC 100 includes a non-volatilememory to beforehand store the data to correct the gain characteristicsof the variable gain amplifiers MVGA and IVGA.

In the embodiments, the second measurement is conducted for calibratingthe output power of the transmitter and uses the load LPF3 to make theoverall loop have only one pole. The third measurement is conducted foramplitude loop gain measurement and adjustment and uses the loop filterLPF2. According to results of the second and third measurement, thecalibration is completed.

In the description, the present invention is applied to a dual-bandsystem capable of conducting communications in two systems including theGSM and CDS 1800 systems. However, the present invention is alsoapplicable to a case of a triple-band system configured forcommunications in the CSM system, the DCS 1800 system, and a personalcommunication system (PCS) 1900 in which communications can be conductedusing phase modulation in the 8-PSK modulation mode in addition to theGMSK modulation mode, and to communications using a 850 MHz band.

It should be further understood by those skilled in the art thatalthough the foregoing description has been made on embodiments of theinvention, the invention is not limited thereto and various changes andmodifications may be made without departing from the spirit of theinvention and the scope of the appended claims.

1-22. (canceled)
 23. A wireless communication apparatus comprising: abaseband circuit which generates first signals to be transmitted; and atransmitter which includes a modulator which modulates the first signalsand generates a modulated signal, a phase detector which detects themodulated signal and outputs a phase control signal, an amplitudedetector which detects the modulated signal and outputs an amplitudecontrol signal, an oscillator which receives the phase control signaland outputs a transmission signal, a power amplifier which receives thetransmission signal and the amplitude signal and outputs an amplifiedtransmission signal, a power detector which detects an output power ofthe amplified transmission signal, a first amplifier which couples thepower detector and the amplitude detector, a second amplifier whichcouples the amplitude detector and the power amplifier, and a gaincontroller which instructs gain information to the first amplifier andthe second amplifier in accordance with a power instruction signal fromthe baseband circuit and controls respective gain in mutually opposingdirections, wherein the transmitter has a register which storescorrection data for correcting the variation of the output powercharacteristic of the power amplifier from the baseband circuit.
 24. Thewireless communication apparatus according to claim 23, wherein thecorrection data stored in the register includes: corrective data tocorrect slope of gain characteristics of the second amplifier circuitwith respect to the power instruction signal; and corrective data tocorrect gain offset of gain characteristics of the second amplifiercircuit with respect to the power instruction signal.
 25. The wirelesscommunication apparatus according to claim 23, wherein the transmitterfurther includes a switching means which receives the power instructionsignal and an output signal of the second amplifier and supplies one ofthe power instruction signal and the output signal in accordance with aninstruction from the baseband circuit, and wherein the power amplifieris controlled by the output signal in a phase and amplitude modulationmode and is controlled by the power instruction signal in a phasemodulation mode.
 26. The wireless communication apparatus according toclaim 23, wherein the register is a nonvolatile memory.
 27. The wirelesscommunication apparatus according to claim 23, wherein the gaincontroller generates a bias current as the gain information for thesecond amplifier circuit according to the correction data stored in theregister.